1. Technical Field
The present invention relates to a dual-modulus prescaler for a RF frequency synthesizer, and more particularly to a dual-modulus prescaler for a RF frequency synthesizer, which may operate in a high speed and reduce energy consumption.
2. Description of the Prior Art
Generally, a radio frequency (RF) synthesizer means a phase locked loop (hereinafter, referred as PLL), which outputs wider-ranged frequency by adjusting values of a programmable counter and is applied mainly to communication systems such as a portable personal mobile communication, an amateur communication, airplane, and so on.
FIG. 1 is a block diagram showing a receiver in the general portable personal mobile communication. As shown in the figure, the receiver includes a low-noise amplifier 10 for linearly amplifying at a predetermined ratio a signal received from a public network through an antenna 1, a variable frequency synthesizer 20 for generating an oscillation signal with a variable frequency, a first mixer 40 for generating a signal with a middle frequency by mixing a frequency of the signal amplified in the low-noise amplifier 10 and a frequency of the output signal of the variable frequency synthesizer 20, a middle frequency amplifier 60 for amplifying the signal with the middle frequency at a predetermined ratio and outputting the amplified signal, a fixed frequency synthesizer 80 for first and second oscillation signals with fixed frequencies, a second mixer 100 for outputting first and second mixed signals by mixing a frequency of the signal amplified in the middle frequency amplifier 60 and a frequency of the signal from the fixed frequency synthesizer 80, a low-pass filter 120 for filtering to pass a low frequency bandwidth of the first and second mixed signals, and an analog-digital (AD) converter 140 for converting an analog signal filtered in the low-pass filter 120 to a digital signal and outputting a baseband signal (BBS).
FIG. 2 is a block diagram for illustrating the general frequency synthesizer 20. As shown in the figure, the frequency synthesizer 20 includes a phase detector 21 for detecting phases of a reference frequency Fr and a feedback input frequency to generate an error signal voltage, a charge pump 22 for pumping a charge according to the error signal voltage, a loop filter 24 for integrating outputs of the charge pump 22 and controlling a PLL loop gain, a voltage controlled oscillator (VCO) 26 for outputting, as a clock signal CLK, a signal in an oscillation frequency Fo controlled in response to an error signal voltage, which eliminates noise from the loop filter 24, and a programmable frequency divider 28 outputting a frequency signal divided at a predetermined ratio in response to the clock signal CLK from the VCO 26 and feeding back the divided frequency signal as an input of the phase detector 21.
The programmable frequency divider 28 includes a dual-modulus prescaler 28a for dividing the clock signal CLK from the VCO in first and second modes with different dividing ratios in response to a feedback counting signal (MC) and outputting the divided clock signal CLK, a first counter 28b for counting clock pulses divided in the dual-modulus prescaler 28a to output the count as an input frequency signal of the phase detector 21, and a second counter 28c for counting clock pulses divided in the dual-modulus prescaler 28a and outputting a mode control signal (MC) according to the count to the dual-modulus prescaler 28a. 
The frequency synthesizer 20 has a configuration that the loop filter 24 and the VCO are attached to outside of a PLL module having the phase detector 21, the charge pump 22 and the programmable frequency divider 28.
In the frequency synthesizer constructed as above, the output frequency Fo becomes a value multiplying the reference frequency Fr by a total dividing ratio (M) which is divided by the programmable frequency divider 28.
Such RF variable frequency synthesizer using a Pulse Swallow Method includes the programmable frequency divider 28 in which a total dividing ratio is M and which is composed of three elements: the dual-modulus prescaler 28a and the first and second counters 28b, 28c. At this time, the output frequency Fo of each element is determined by combinations of programmed counts of the elements.
Provided that a dividing ratio of the dual-modulus prescaler 28a is P and counts of the first and second counters 28b, 28c are respectively N and S, the output frequency Fo is calculated as follows.                                                                         F                o                            =                              M_F                r                                                                                        =                                                (                                      P_N                    +                    S                                    )                                ⁢                                  F                  r                                                                                        Equation        ⁢                  xe2x80x83                ⁢        1            
where,
P=2n, (n=1, 2, - - - ) 
S=0xcx9c(Pxe2x88x921)
Nxe2x89xa7S.
The dual-modulus prescaler 28a at first divides the CLK frequency of the VCO 26 in the first and second modes having different dividing rates, for example P and P+1. In fact that the VCO 26 operates in the highest frequency in the frequency synthesizer, the dual-modulus prescaler 28a also requires high speed operation.
Such high speed operation consumes much energy and the prescaler 28a occupies most of the power consumed in the PPL module.
Therefore, the high speed operation and low energy consumption of the prescaler 28a is needed to the RF synthesizer for the mobile communications.
The prescaler 28a currently used is implemented in a shift register ring method.
FIG. 3 is a block diagram showing the conventional prescaler 28a employing the shift register ring method. As shown in the figure, the prescaler 28a includes a high speed synchronous divider 28a-1 operating at a 4/5 dividing rate, a low speed asynchronous divider 28a-2 operating at a 32 dividing rate, and a logic gate 28a-3.
The synchronous divider 28a-1 includes first to third flip-flops FF1-FF3 which is synchronous with the CLK of the VCO 26, an inverter INV for inverting an output of the first flip-flop, a first NAND gate (ND1) for inverted-AND operating an output signal of the inverter INV and an inputted control signal CTR and outputting the operated signal as an input of the second flip-flop FF2, and a second NAND gate (ND2) for inverted-AND operating the output signals of the first and second flip-flops FF1, FF2 and outputs the operated signals as inputs of the third flip-flop FF3.
The output signal of the third flip-flop FF3 is fed back as an input of the first flip-flop FF1 as well as used as a synchronous signal of the asynchronous divider 28a-2.
The asynchronous divider 28a -2 includes five two-dividing flip-flops (FF4-FF8) for supplying an output Q as a synchronous signal of the next flip-flop and feeding back an inverse output /Q as an input thereof. The fourth flip-flop FF4 is synchronous with an output signal of the third flip-flop FF3.
The logic gate 28a-3 includes an AND gate for AND operating output signals of the two-dividing flip-flops FF4-FF8 and a mode control signal MC from the second counter 28c. 
Operation of the dual-modulus prescaler 28a employing the shift register ring method and constructed is explained below with reference to a timing diagram in FIG. 4.
The dual-modulus prescaler 28a selects a dividing rate according to a logic level of the mode control signal MC, which can be P or P+1. In other words, the dividing ratio is P when the mode control signal MC is a logic level xe2x80x9clowxe2x80x9d, or else the dividing ratio is P+1.
At first, a dividing operation at P(=27=128) is same as a ripple counter. That is, because the AND gate of the decoder 28a-3 always outputs low when the mode control signal MC is selected as a logic level xe2x80x9clowxe2x80x9d, the control signal CTR become a logic level xe2x80x9clowxe2x80x9d. If the signal is inputted to the first and second ANAD gates ND1, ND2 of the synchronous divider 28a-1, the NAND gates output a logic level xe2x80x9chighxe2x80x9d. As a result, the synchronous divider 28a-1 becomes a four-divider having two flip-flops and an inverter. Therefore, as shown in FIG. 4, the synchronous divider 28a-1 operates in a four dividing mode (/4mode), which maintains one cycle for every four clock cycles (4CLK).
A 4-divided output of the synchronous divider 28a-1 is supplied to the asynchronous divider 28a-2, which operation division at a 32 dividing ratio, as a synchronous signal. Therefore, the asynchronous divider 28a-2, obtains a 128-divided signal.
Next, in a dividing operation at P+1(=27+1=129), if outputs of all flip-flops FF4-FF8 of the asynchronous divider 28a-2, in state that a logic level of the mode control signal MC is xe2x80x9chighxe2x80x9d, the control signal CTR maintains a logic level xe2x80x9chighxe2x80x9d during 4 cycles of the clock CLK. If the signal is inputted to the first and second NAND gates ND1, ND2 of the synchronous divider 28a-1, the NAND gates operate like the inverter, resulting in 5-divider having three flip-flops, an inverter and a NAND gate. Therefore, the P+1 divider operates in a 5-dividing mode only for 4 clock cycles, as shown in FIG. 4.
When comparing a result of the 5-dividing mode with the 4-dividing mode, the 5-dividing mode becomes identical to the 4-dividing mode when delaying a logic level xe2x80x9chighxe2x80x9d signal of the 4-dividing mode as much as one cycle. When taking over the signal to the next asynchronous divider 28a-2, 1 clock cycle (1CLK) is delayed to obtain 129-divided signal.
However, such conventional dual-modulus prescaler employs many flip-flops, or 1 to 3 flip-flops, operated by an output frequency of a high speed VCO, which requires a large amount of energy for each flip-flops. In addition, because a drive capability of the VCO is limited due to abundant loads for each flip-flop, the prescaler requires more power. Moreover, a load amount, which the first flip-flop should drive, is more than that of a general asynchronous divider.
In addition, in the conventional dual-modulus prescaler, logic gates of the synchronous divider for making the P+1 dividing are used as delay elements. That is, the suitable P+1 dividing operation can be obtained only when a delay generated in the first flip-flop have an equational relation with a delay generated in the inverter and the first NAND gate during one cycle.                                           t            dFF1                    +                      t            dINV                    +                      t            dND1                           less than         T                            Equation        ⁢                  xe2x80x83                ⁢        2            
where T is a clock cycle, tdFF1 is a delay time of the first flip-flop, tdINV is a delay time of the inverter and tdND1 is a delay time of the first NAND gate.
Furthermore, in the prior art, the synchronous divider generates delays twice as much as the asynchronous divider.
The present invention is designed to overcome drawbacks of the prior art. An object of the present invention is to provide a dual-modulus prescaler for a RF synthesizer, which may give more improved characteristics in operation rate and energy consumption aspects by implementing the dual-modulus prescaler, which is one component of the PPL module, with use of a selective latch technique which makes a selective latch latching a feedback signal thereof in an area where a latch control signal is enabled and makes a clock pulse from a voltage controlled oscillator passing as it is.
In order to accomplish the above object, the present invention provides a dual-modulus prescaler for a RF (Radio Frequency) synthesizer which has a voltage controlled oscillator (VCO) for generating a clock signal and a programmable counter for generating a mode control signal to select a frequency-dividing mode, the dual-modulus prescaler comprising a first frequency-dividing circuit for being synchronized to the clock signal to generate a latch control signal, latching the clock signal at a leading edge of the generated latch control signal, changing the frequency-dividing mode from a first frequency-dividing mode to a second frequency-dividing mode when latching the clock signal, and frequency-dividing and outputting the clock signal; a second frequency-dividing circuit for frequency-dividing the frequency divided signal from the first frequency-dividing circuit at a predetermined frequency-dividing ratio and outputting a plurality of frequency divided signals; and a logic operation circuit for logically operating a plurality of the frequency divided signals and the mode control signal to control the dividing mode of the first frequency-dividing circuit.
The first frequency-dividing circuit may include a first flip-flop circuit for being synchronized to the clock signal to generate the latch control signal; a latch for selectively latching the clock signal in a predetermined cycle of the clock signal at the leading edge of the latch control signal; a second flip-flop circuit for frequency-dividing an output signal of the latch at a predetermined frequency-dividing ratio to generate a first frequency divided signal; a third flip-flop for frequency-dividing the first frequency divided signal at a predetermined frequency-dividing ratio to output second and third frequency divided signals; and a first AND gate for AND operating the second and third frequency divided signals and the frequency-dividing mode control signal from the logic operation circuit to output the operated signal to an input terminal of the first flip-flop.
The latch preferably feeds back an output signal as an input thereof.
The second flip-flop may generate the first frequency divided signal, made by two frequency-dividing an output signal of the latch in response to a falling edge of the output signal of the latch.
The second flip-flop preferably feeds back an inverted output signal as an input thereof.
The third flip-flop may output the second frequency divided signal, which is made by dividing by two the first frequency divided signal in response to a falling edge of the first frequency divided signal, and the third frequency divided signal, which is made by delaying the second frequency divided signal as much as a half cycle.
The third flip-flop preferably feeds back an inverted output signal of the first frequency divided signal as an input thereof.
The second frequency-dividing circuit may include a plurality of stages of asynchronous flip-flop circuits, which sequentially divide the second frequency divided signal at a predetermined frequency-dividing ratio and output a plurality of the frequency divided signals.
Preferably, one flip-flop of a plurality of the flip-flops outputs an output signal to a synchronous signal input terminal of a next flip-flop, and feeds back an inverted output signal to an input terminal of the flip-flop itself.
The first frequency-dividing circuit may perform a four frequency-dividing mode operation when the output signal of the first AND gate is in a first logic level, and perform a five frequency-dividing mode operation when the output signal of the first AND gate is enabled to a second logic level.
The logic operation circuit may include a second AND gate for AND operating a plurality of frequency divided signals from the second frequency-dividing circuit and the frequency-dividing mode control signal.